The present invention relates to a semiconductor device and a manufacturing method thereof, and, more particularly, to a manufacturing method of manufacturing a semiconductor device which includes a step of forming a dummy gate.
To implement a higher performance and lower cost of a semiconductor integrated circuit using MOS transistors, miniaturization of devices is important. The miniaturization of devices, which can be accomplished by using the STI (Shallow Trench Isolation) technique, faces a problem of an increased wiring resistance. To overcome this problem, a scheme of reducing the wiring resistance using a metal material of a low resistance for the gate electrode has been proposed.
In a conventional case where a source/drain region is formed after forming a gate insulator film and a gate electrode, a high temperature treatment and thermal oxididation are required, which raise such problems as the increased resistance of the metal electrode and deterioration of the reliability of the gate insulator film.
As means of overcoming those problems, a step of forming a source/drain region, which involves a high temperature treatment, is carried out prior to burying the gate insulator film and gate electrode in a groove which is self-aligned with the source/drain region.
Referring to FIGS. 1A through 1I, 2A and 2B, one example of this technique (Jpn. Pat. Appln. No. 8-356493) will be discussed below. FIGS. 1A through 1I illustrate the cross-section of a transistor in a gate length direction (channel length direction), and FIGS. 2A and 2B illustrate the cross-section of the transistor in a gate width direction (channel width direction).
First, using the shallow trench isolation (STI) technique, a transistor-forming region 502 and an isolation region 503 are formed on an Si substrate 501 (FIGS. 1A and 2A).
Next, an SiO.sub.2 film 504 of about 10 nm in thickness is formed on the exposed surface of the Si substrate 501, and a poly Si film for a dummy gate pattern is deposited about 300 nm thick on this SiO.sub.2 film 504 and is processed to form a dummy gate pattern 505 using, for example, lithography and RIE (FIG. 1B).
Then, with the dummy gate pattern 505 used as a mask, phosphorous ions, for example, are injected in a device region surrounded by the isolation region 503 to form an n.sup.- type diffusion region 506 (FIG. 1C).
After an Si.sub.3 N.sub.4 film is deposited on the entire surface, RIE is performed on the entire surface to form an Si.sub.3 N.sub.4 film 507 with a thickness of approximately 20 nm on the side wall of the dummy gate pattern 505 (FIG. 1D).
Then, with the dummy gate pattern 505 and the Si.sub.3 N.sub.4 film 507 used as masks, arsenic ions, for example, are injected in the n.sup.- type diffusion region 506, forming an n.sup.+ type diffusion region 508, thus forming or a so-called LDD (Lightly Doped Drain) structure (FIG. 1E).
Next, a CVD-SiO.sub.2 film 509 is deposited, for example, about 300 nm thick on the entire surface, and is densified for approximately 30 minutes in the N.sub.2 atmosphere at about 800.degree. C., after which the entire surface is flattened by CMP (Chemical Mechanical Polishing) to expose the surface of the dummy gate pattern 505 (FIG. 1F).
Then, the dummy gate pattern 505 is selectively removed to form a groove 510, after which with a resist film (not shown) formed on a desired region, an interlayer film (SiO.sub.2 film 509 ) and a sidewall insulator film (Si.sub.3 N.sub.4 film 507 ) used as masks, ion injection is carried out only in the channel reserved region under the groove 510. The activation of this channel impurity is implemented by a heat treatment at 800.degree. C. for about 10 seconds using RTA, for example, thereby forming a channel impurity region 511 (FIG. 1G).
Then, the SiO.sub.2 film 504 at the bottom of the groove 510 is removed (FIGS. 1H and 2B).
Next, a high dielectric film, such as a Ta.sub.2 O.sub.5 film, is deposited about 20 nm thick as a gate insulator film 512 on the entire surface, followed by deposition of a metal film of Ru or the like on the entire surface as a gate electrode 513. Thereafter, CMP is performed on the entire surface to leave the metal electrode 513 and the high-dielectric gate film 512 buried in the groove 510 (FIG. 1I).
Thereafter, after an SiO.sub.2 film is deposited about 200 nm thick as an interlayer insulator film on the entire surface, contact holes to the source and drain regions and the gate electrode are formed in the interlayer insulator film, then an Al layer is formed on the entire surface and patterned to form Al wiring. Then, a passivation film is deposited on the entire surface, which completes the basic structure of a transistor.
Since this method however exposes the end portions of the isolation region twice as shown in FIGS. 2A and 2B, etching with, for example, a fluorine-based etching solution would form large dents at those portions, thus exposing the edge corners of the device region. As a result, an electric field is concentrated on the edge corners, resulting in deterioration of the transistor characteristics, such as a lower reliability of the gate insulator film.
In the conventional transistor manufacturing method which forms a source/drain region using a dummy gate pattern and then forming a gate insulator film and a gate electrode in a groove formed by removing the dummy gate pattern, large dents are formed at the edge corners of the isolation region, exposing the edge corners of the device region, so that an electric field is concentrated on the edge corners, deteriorating the transistor characteristics.
A description will now be given of other problems of a manufacturing process for an MOS transistor using a dummy gate.
The first problem will be discussed below.
In a manufacturing process for MOS transistor to be used in a DRAM or the like, as shown in FIG. 3A, a sidewall insulator film 507 having an etching-resistive property is formed on the side surface of a dummy gate 505, so that even with slight misalignment at the time of forming contact holes to the gate electrode and the source and drain regions in an interlayer insulator film which will be formed later, the sidewall insulator film 507 prevents the gate electrode and the source/drain region from being short-circuited and thus improves the integration density.
In a manufacturing process for damascene gate transistors, conventionally, to form the sidewall insulator film 507 on the side surface (where an oxide film is formed) of the dummy gate 505, which is comprised of an amorphous silicon film 505a and a silicon nitride film 505b, the height of the sidewall insulator film 507 should be controlled by RIE that is carried out to form the sidewall insulator film 507, at the time of performing CMP on the interlayer insulator film, so that the sidewall insulator film 507 will not be exposed when the CMP is completed.
When the sidewall insulator film 507 is exposed upon completion of CMP as shown in FIG. 3B, however, the sidewall insulator film 507 may be removed at the time of removing the dummy gate 505 as shown in FIG. 3C. That is, the margin for a fluctuation in etching result was low.
In the case of ordinary transistors, when a silicon nitride film is used as an etching stopper to be formed on the gate electrode and the sidewall insulator film 507 of the gate electrode, the parasitic capacitance may not become low enough to meet the requirements of ultra-miniaturization and fast operation because the dielectric constant of the silicon nitride film is not so low.
The second problem will be discussed below.
In the manufacturing process for damascene gate transistors, since the dummy gate also serves as a CMP stopper at the time of flattening the interlayer insulator film, the silicon nitride film 505b is used for the dummy gate (FIG. 4A) as in the example illustrated in FIGS. 3A-3C. Normally, a silicon nitride film 520 is a typical liner to be formed on the side wall of the dummy gate 505. In the case of damascene gate transistors, however, the gate liner 520 is also etched at the time of removing the dummy gate.
Thereafter, at the time of the polycrystalline or amorphous silicon film 505a, the lower layer of the dummy gate, is removed (FIG. 4C), and removing the silicon oxide film 504 which has been used as a buffer, the upper portion of the groove where the gate is to be formed becomes widened by the size t of the dummy gate 505 due to no liner or silicon nitride film 520 present (FIG. 4D).
The finer the miniaturization of individual semiconductor devices in a semiconductor integrated circuit becomes and the higher the integration gets, the larger the memory capacity can become. The above-described prior art however sets the size of actual completed transistors wider than the designed width of the dummy gate, which is disadvantageous for device miniaturization.
If the thickness of the buffer oxide film of the dummy gate is 10 nm and the width of the liner of the silicon nitride film is 15 nm, for example, the transistor size becomes 28 nm, which is 15 nm, the designed gate size the liner thickness, plus the widened amount of 10 nm.times.1.3=13 nm of the buried insulator film around the gate at the time the buffer oxide film is separated. For transistors of the 0.1 .mu.m generation, this means that the portion where the gate lines run adjacent to one another becomes narrower by 28 nm.times.2=56 nm with respect to the distance of 0.2 .mu.m between gate lines. This is disadvantageous in implementing a high-frequency operation in consideration of the interline capacitance.
The wider transistor size also reduces a margin for patterning the interlayer insulator film for forming contacts in the source and drain regions, so that the minimum design size should be set larger accordingly, which is also disadvantageous in implementing a higher integration density.
To overcome the widening of the upper portion of the gate line, overetching should be performed by CMP or the like to the level where the gate's groove is not widened. This cannot ensure a sufficient gate height; in a case where the dummy gate is comprised of a polycrystalline film of 200 nm in thickness and a silicon nitride film of 200 nm in thickness, for example, the gate height after the formation of the gate becomes very low. Consequently, the resistance of the gate line becomes higher, resulting in increased dissipation power and impaired dielectric characteristic.
The third problem will be discussed below.
Miniaturization of, particularly, MOSFET devices using silicon has rapidly progressed since the use of polycrystalline silicon as a material for the gate electrode. The manufacturing process for metal gate transistors which had been used before the use of polycrystalline silicon will be discussed below with reference to FIGS. 5A to 5D.
First, an isolation region 602 and a p-type diffusion layer 603 are formed on a silicon substrate 601 (FIG. 5A). Then, with a photoresist 604 as a mask, ions of an n-type impurity like arsenic are injected to form an n-type diffusion layer (source/drain region) 605 (FIG. 5B).
After the impurity doped in the n-type diffusion layer (source/drain region) 605 is activated by a heat treatment at 900.degree. C. or higher, the surface of the silicon substrate 601 is oxidized by thermal oxidization, forming a silicon oxide film 606 on which a metal layer 607 of aluminum or the like is deposited. This metal layer 607 is so patterned by photolithography as to leave the area surrounded by the n-type diffusion layer (source/drain region) 605, thus forming a metal gate electrode 607.
Finally, an insulator film 608 such as a silicon oxide film is deposited on the entire surface, contact holes are bored, and a metal wiring layer 609 is formed, thus completing a transistor.
This process requires that steps up to the activation of the source/drain diffusion layer 605 should be finished before forming the metal gate electrode 607, so that the positional relation between the source/drain diffusion layer 605 and the gate electrode 607 is determined by the photolithography step. As shown in FIG. 5C, therefore, the source/drain diffusion layer 605 and the gate electrode 607 need to be overlap each other by the alignment margin "d" in the photolithography step. Because this process cannot employ a so-called LDD structure which has a lighter impurity concentration of the diffusion layer at the gate's edge portions at a shallower depth, it is difficult to suppress a short channel effect.
Because of those reasons, polycrystalline silicon which has a higher heat resistivity and is easier for micro-processing than metal like aluminum has been used for the gate electrode. One example of a manufacturing method for transistors using polycrystalline silicon for the gate electrode will now be described referring to FIGS. 6A through 6D.
First, an isolation region 702 and a p-type diffusion layer 703 are formed on a silicon substrate 701 (FIG. 6A).
Next, the surface of the silicon substrate 701 is oxidized by thermal oxidization, forming a silicon oxide film 704 on which a polycrystalline silicon layer 705 is deposited. This polycrystalline silicon layer 705 is patterned by photolithography to form a gate electrode 705, and the surface of the silicon substrate 701 and the area around the polycrystalline silicon layer 705 are oxidized by thermal oxidization, forming a silicon oxide film 706. Then, ion injection of an n-type impurity like arsenic is carried out and the impurity is activated by a heat treatment at 900.degree. C. or higher to form a shallow n-type diffusion layer (LDD region) 707 with a relatively low impurity concentration (FIG. 6B).
An insulator film like a silicon oxide film is deposited on the entire surface, after which anisotropic etching is performed to form a silicon oxide side wall 708 on the side wall of the polycrystalline silicon gate electrode 705. With the gate electrode 705 and the silicon oxide side wall 708 used as masks, ion injection and activation of the impurity by a heat treatment at 900.degree. C. or higher are implemented again, forming an n.sup.+ impurity diffusion layer (source/drain region) 709, and the polycrystalline silicon gate electrode 705 is doped to an n.sup.+ type (FIG. 6C).
Finally, an insulator film 710 such as a silicon oxide film is deposited on the entire surface, contact holes are bored, and a metal wiring layer 711 is formed, thus completing a transistor (FIG. 6D).
This process, as compared with the process illustrated in FIGS. 5A-5D, not only improves the processability of the gate electrode but can also ensure self-alignment of the gate electrode and the source/drain diffusion layer because ion injection and activation of the impurity can be carried out with the polycrystalline gate electrode used as a mask, thus requiring no margin for the alignment in the photolithography step. Further, it is easy to use a so-called LDD structure which has a lighter impurity concentration of the diffusion layer at the gate's edge portions at a shallower depth, as a measure against a short channel effect which is originated from miniaturization of devices.
As the recent device miniaturization progresses to fabricate transistors with a gate length of 0.1 .mu.m or shorter, however, the parasitic resistance of the polycrystalline silicon gate electrode becomes too large to be neglected, deteriorating the device performance. To overcome this problem, a low-resistance material should be used for the gate electrode and its use for the gate electrode becomes desirable again. Since the manufacturing method as shown in FIGS. 5A-5D has a difficulty in manufacturing ultra-small devices as mentioned earlier, there is a demand for a process which can ensure self-alignment of the source/drain diffusion layer and the gate electrode and forms the gate electrode after activation of the source/drain diffusion layer is completed.
Although the silicon oxide film formed by thermal oxidization has been used as the gate insulator film in today's transistors, the generation of transistors with a gate length of 0.1 .mu.m or shorter requires a very thin gate insulator film, 5 nm or thinner, so that the tunnel current may be produced. To overcome this problem, a high-dielectric film like a tantalum oxide film (Ta.sub.2 O.sub.5) which has a higher dielectric constant than the silicon oxide film should be used to increase the physical film thickness. Even this high-dielectric film like a tantalum oxide film should avoid a heat treatment for impurity activation from the viewpoint of the heat resistivity. It is therefore desirable to form the gate insulator film after forming the source/drain diffusion layer.
To meet those requirements, a transistor manufacturing process as illustrated in FIGS. 7A to 7H has been proposed.
An isolation region 802 and a p-type diffusion layer 803 are formed on a silicon substrate 801 (FIG. 7A).
Then, the surface of the silicon substrate 801 is oxidized by thermal oxidization to form a silicon oxide film 804 on which a silicon nitride film 805 is deposited and patterned to form a dummy gate electrode. with this dummy gate 805 used a mask, ions of an n-type impurity like arsenic are injected in the p-type diffusion layer 803 and the impurity is activated by a heat treatment at 900.degree. C. or higher, forming an n.sup.- type LDD diffusion layer 806 (FIG. 7B).
A silicon oxide film is deposited on the entire surface and anisotropic etching is carried out to form a silicon oxide side wall 807 on the side wall of the dummy gate 805 of silicon nitride. With the gate electrode 805 and the silicon oxide side wall 807 used as masks, ion injection and activation of the impurity by a heat treatment at 900.degree. C. or higher are implemented again, forming an n.sup.+ impurity diffusion layer (source/drain region) 808 (FIG. 7C).
Next, a silicon oxide film 809 is deposited on the entire surface and is polished to be flattened by using the dummy gate 805 of silicon nitride as a stopper. Silicon nitride is desirable as a material for the dummy gate, which is used as a stopper in polishing the silicon oxide film 809 (FIG. 7D).
The exposed silicon nitride film 805 is removed by a treatment using hot phosphorus or the like, thereby forming a groove in the gate-electrode forming region (FIG. 7E).
Further, the silicon oxide film 804 remaining in the groove is etched out by hydrofluoric acid or the like, exposing the surface of the silicon substrate 801 (FIG. 7F).
A high-dielectric film 810 like tantalum oxide film is deposited on the entire surface, then a titanium nitride film 811 as a diffusion barrier layer and an aluminum layer 812 as the gate electrode are deposited, the aluminum film and the titanium nitride film located outside the groove are removed by CMP or the like (FIG. 7G).
A silicon oxide film 813 is deposited on the entire surface, then contact holes are bored and a metal wiring layer 814 is formed, completing a transistor (FIG. 7H).
The above-described process can form the gate electrode of a low-resistance metal after forming the source/drain diffusion layer and can self-align the source/drain diffusion layer and the gate electrode.
This process however causes the width (L') of the groove to become wider than the size (L) of the dummy gate pattern, initially formed by miniaturization, at the time of removing the dummy gate 805 and exposing the silicon substrate 801 as shown in FIG. 7F. This makes it difficult to form ultra-small gates. This problem appears to be able to be overcome by using an insulator material which has an etching selectivity with the silicon nitride film, the material for the dummy gate 805, and the silicon oxide film 804 underlying the lower portion of the dummy gate electrode, for the sidewall insulator film 807 and the buried material 810 around the dummy gate pattern. The new use of a material having such a property in the semiconductor manufacturing process involves significant difficulty.
In a MOS transistor which uses a silicon oxide film (SiO.sub.2 film) as a gate oxide film, making the gate oxide film thinner plays an important role in suppressing the short channel effect of the transistor. Making the gate oxide film thinner than the level at which direct tunneling occurs (e.g., a thickness smaller than about 3 nm) is considered inappropriate from the viewpoint of the reliability of transistors.
The conventional polycide gate structure (the lamination of a polysilicon film and a silicide film), as the width of the gate electrode becomes narrower, the thickness of the gate electrode becomes thicker, undesirably increasing the steps of the gate electrode.
As solutions to those shortcomings, various schemes have been proposed, such as the use of a metal gate electrode and the use of a high-dielectric film like a Ta.sub.2 O.sub.5 film to reduce the equivalent thickness of the oxide film while suppressing the leak current (direct tunneling).
However, the metal gate electrode is not a good choice in view of the heat resistivity. An MOS transistor using a high-dielectric film as the gate insulator film faces the following problems.
Through a high-temperature treatment at 800 to 1000.degree. C. after the formation of the gate insulator film (high-dielectric film) (e.g., formation of the source/drain diffusion layer or reflowing of the interlayer insulator film), the interface reaction between the silicon substrate and the gate insulator film or the interface reaction between the gate insulator film and the gate electrode occurs.
It is however difficult for the gate insulator film (high-dielectric film) to endure such a high-temperature treatment. This results in deterioration of the gate insulator film, making it difficult to provide MOS transistors with good electric characteristics.
As another solution has been proposed an MOS transistor with a groove channel structure (e.g., in "Groove Gate MOSFET," 8th Conf. On Solid State Device, pp. 179-183, 1976 by Nishimatsu et al.).
FIG. 8 shows the cross section of a conventional MOS transistor with a groove channel structure. In the diagram, "901" is a p-type silicon substrate, "9022 is an isolation region (STI), "9032 is a gate insulator film, "904" is an LDD, "905" is a source/drain diffusion layer with a high impurity concentration, "906" is an interlayer insulator film, "970" is a gate electrode (polysilicon film) and "908" is a source/drain line electrode.
In this type of MOS transistor, as the gate electrode 907 extends over the source/drain diffusion layer 905, it is necessary to prevent the gate electrode 907 and the source/drain line electrode 908 from being short-circuited due to, for example, misalignment.
This may be avoided by putting some distance between the gate electrode 907 and the source/drain line electrode 908, which however becomes a bottleneck in ultra-miniaturization of devices.
Because the silicon surface of the recess which is formed by etching the silicon substrate 901 is used as a channel, an etching damage should be removed. As it is difficult to remove such an etching damage, the device characteristics will not be improved as expected.
In the conventional MOS transistor with a groove channel structure, as apparent from the above, the gate electrode extends over the source/drain diffusion layer, it is necessary to put some distance between the gate electrode and the source/drain line electrode, which makes ultra-miniaturization of devices difficult.
With the conventional gate structure of polycide (lamination of a polysilicon film and a silicide film), as the width of the gate electrode becomes narrower, the thickness of the gate electrode is increased to reduce the wiring resistance of the gate electrode. As the size of the gate electrode in the direction of the channel length (L) becomes smaller, therefore, the step of the gate electrode increases. This raises such a problem that the aspect ratio of a contact hole becomes larger at the time of forming the contact hole in the gate electrode.